I currently use a board that has 32-bit wide 10ns SRAM. It is so simple that I can just write to it asynchronously. However, this board isn't produced anymore so I'm looking for a replacement. The Saturn board would work but I'm nervous about using DDR memory. One of the things the system does is essentially motion detection. It stores a background image and compares the current image to it, pixel by pixel. How would I do this using DDR memory? I read that you have to copy a row of it at a time to block ram and then access whatever you want from block ram. More specifically, what are the number of clock cycles required for in-order reads vs random reads, and for in-order writes and random writes?
Hi, I suggest that you can use the Coregen to generate a DDR controller(MCB) first, run the built-in simulation, and then look at ug388.pdf to understand the MCB control flow, use it as a template to design your own scripts, so you should be able to assess the DDR Whether it meets your needs. You don't need to understand how DDR works because Xilinx create a simple interface for users. In addition, this forum seems not update for a long time...
